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1. Reduced etch rates. This problem can be caused by operating conditions, solution imbalance, or chloride contamination. 2. Under- and overetching. A review of etching conditions, solution control, and the resist stripping process may show deviations from normal. In the case of immersion etching, the solution and panel agitation may need to be increased.When spray-etching, a check of nozzles and line clogging is indicated. 3. Temperature changes. Recirculating water rates and thermostats need to be examined regularly. Overheating may be due to high copper content, contamination, or rapid peroxide decomposition. 4. Copper sulfate recovery stoppage. Examine solution balance, heat exchanger, and other recovery equipment. Exit conveyor jamming difficulties from thermal excursions and varying crystal size and liquid content cause major shop floor problems.

10.25s + 1 1 FIGURE P13-7 13.8. For the control system shown in Fig. P13.8, determine: (4 C(sYNs) (b) C(w) (c) offset (4 W.5) (e) whether the closed-loop response is oscillatory

substrate, thereby saving valuable module space and reducing interconnect distance, but such system configuration can increase the risk of reliability performance of the system. Direct die attachment can be accomplished by conventional die attach/wire bonding, tape-automated bonding (TAB), and flip-chip processes. Lead-free requirements impose the following additional requirements:

Use of suitable lead-free materials in the assembly bill-of-materials Compatibility of these materials with lead-free processing temperatures

FIGURE Pl3-8

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Performance of the package moisture sensitivity level (MSL) can be impaired by the higher temperature compatibility arising from lead-free requirements 4631 Wire Bond For most part, transition to lead-free of a wirebond package on a component level is relatively straightforward Through the use of gold wires, the first level interconnect is already lead-free Further, most of the metal lead-frame-based packages are lead-free-compliant as long as the mold compound or the die-attach materials are free of lead or similar components and are able to withstand the higher temperatures seen by the package during component reflow BGA-based wirebond packages, on the other hand, additionally need use of lead-free BGA balls on the package to make it compatible with leadfree requirements 4632 Tape-Automated Bonding (TAB).

TAB is rather expensive because it requires a custom tape for each different IC and its construction requires a significant amount of processing Furthermore, the assembly process is equipment-intensive because of testing of the IC while it is mounted on the tape, excising the IC from the tape and shaping (forming) its leads prior to mounting it onto a substrate, requiring a custom die for gang bonding However, it is attractive because it provides the opportunity to perform burn-in and die testing prior to final assembly The TAB process is schematically illustrated in Fig 410 TAB packages are usually naturally lead-free at the component level Assembly to the application board does require lead-free solder along with a requirement for the package to be able to withstand the high temperatures associated with lead-free processing 4633 Flip-Chip Bonding.

s(s+l)

The flip-chip assembly technique is one of the important techniques of die attach to either the carrier (substrate) or directly to the board usually employing either solder bumps or z-axis conductive polymers Another common mode of attaching silicon dice in the flip-chip configuration is stud bumping, where a gold wire is used in a similar fashion as in wirebonding, but the wire is truncated after establishing contact to the die pads The resultant stud is then flattened using a coining process The original flip-chip assembly, pioneered by IBM, eliminates all the packaging area that is not occupied by the die itself, generally resulting in the smallest footprint and the lowest profile However, wirebonded devices can be back-ground to reduce the overall package thickness It is not trivial to perform a similar back-grinding operation on flip-chip devices for two reasons.

First, the bumping process prefers to use full thickness wafers due to breakage concerns, and second, it is extremely difficult to back-grind bumped wafers In general, flip-chip assemblies can use either grid arrays or peripheral pads for I/O connection at pitches between 01 and 065 mm, but are limited mostly by routing constraints through substrate manufacturing capabilities Consequently, most flip-chip devices in production today use a solder bump area-array pitch in the range of about 015 025 mm Of all the techniques available, flip-chip assembly offers the highest packaging density and there is increased use of flip-chip attachment Consequently, many bumping contractors also offer redistribution services Although redistribution is done on the chip (actually on the wafer), it is considered a packaging operation Additional requirements presented by the need for lead-free, RoHS-compliant, green packages call for lead-free solder bumps.

FIGURE P13-9

Devices that use gold stud bumps previously referenced are.

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